Complementary metal-oxide-semiconductor (CMOS) logic has long been an essential technology for integrated circuits. CMOS transistors implemented for high performance can provide a full rail-to-rail swing while exhibiting very low power consumption. But there are a wide variety of field effect transistor (FET) and logic gate implementations that do not require such high performance and for these cost is often an increasingly stringent consideration. Visual displays and other large area/flexible electronics applications are examples of some typical lower performance but cost sensitive CMOS deployments. In many such lower performance deployments n-channel and p-channel FETs may not both be available, for example hydrogenated amorphous silicon (a-Si:H, often used in thin-film solar cells) metal-oxide and various organic thin-film transistors may support only n-FETs or p-FETS but not both on the same chip. Even where both n-FETs and p-FETs might be technically available such as with certain organic materials and low temperature polysilicon, the cost and complexity of integrating n-FETs with p-FETS on a chip can be significantly higher than implementing the necessary logic using only n-FETs or p-FETs.
There is also non-complementary logic and in this regard FIGS. 1A-B illustrate non-complementary NOT logic gates; FIG. 1A is a NMOS implementation and FIG. 1B a PMOS implementation. The input is marked a, and the inverted output is marked F; disposition of the resistor distinguishes the NMOS from the PMOS implementation of a NOT gate. This resistive-drain circuit uses a single transistor and so it can be fabricated at low cost, but the fact that current flows through the resistor in one or the other of the possible input states results in reduced switching (operating) speed and increased power consumption.
Further in the non-complementary category, FIG. 1C illustrates a pseudo NMOS-NOT gate that avoids the resistor along with its inherent drawbacks at the cost of an additional transistor.
More fundamentally, non-complementary logic typically lacks the full rail-to-rail swing that can be obtained by CMOS logic. FIG. 1D is the voltage transfer function for the pseudo NMOS-NOT circuit of FIG. 1C, and illustrates such an incomplete voltage swing in that VOL is always greater than ground voltage. It is this lack of full swing that can hamper the cascading of logic units with one another which is a typical practice for large-area and flexible electronics. As a result of this the sequential logic of cascaded non-complementary gates can in practice vary from what the idealized per-gate truth tables would predict across the sequence.